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Contents - 10
15.3.1
Non-Maskable Interrupt (NMI)................................................................................ 15-3
15.3.2
Maskable Interrupts.................................................................................................. 15-5
(1)
Interrupt request registers (IRQ0 to IRQ4) .............................................................. 15-5
(2)
Interrupt enable registers (IE0 to IE4)...................................................................... 15-5
(3)
Master interrupt enable flag (MIE) .......................................................................... 15-5
(4)
Master interrupt priority flag (MIPF)....................................................................... 15-5
(5)
Interrupt priority control registers (IP0, IP2 to IP9)................................................. 15-6
15.3.3
Priority Control of Maskable Interrupts ................................................................. 15-10
15.4 IRQ, IE and IP Register Configurations for Each Interrupt ........................................... 15-12
15.4.1
Interrupt Request Registers (IRQ0 to IRQ4).......................................................... 15-12
(1)
Interrupt request register 0 (IRQ0)......................................................................... 15-12
(2)
Interrupt request register 1 (IRQ1)......................................................................... 15-13
(3)
Interrupt request register 2 (IRQ2)......................................................................... 15-14
(4)
Interrupt request register 3 (IRQ3)......................................................................... 15-15
(5)
Interrupt request register 4 (IRQ4)......................................................................... 15-16
15.4.2
Interrupt Enable Registers (IE0 to IE4).................................................................. 15-17
(1)
Interrupt enable register 0 (IE0)............................................................................. 15-17
(2)
Interrupt enable register 1 (IE1)............................................................................. 15-18
(3)
Interrupt enable register 2 (IE2)............................................................................. 15-19
(4)
Interrupt enable register 3 (IE3)............................................................................. 15-20
(5)
Interrupt enable register 4 (IE4)............................................................................. 15-21
15.4.3
Interrupt Priority Control Registers (IP0, IP2 to IP9) ............................................ 15-22
(1)
Interrupt priority control register 0 (IP0) ............................................................... 15-22
(2)
Interrupt priority control register 2 (IP2) ............................................................... 15-23
(3)
Interrupt priority control register 3 (IP3) ............................................................... 15-24
(4)
Interrupt priority control register 4 (IP4) ............................................................... 15-25
(5)
Interrupt priority control register 5 (IP5) ............................................................... 15-26
(6)
Interrupt priority control register 6 (IP6) ............................................................... 15-27
(7)
Interrupt priority control register 7 (IP7) ............................................................... 15-28
(8)
Interrupt priority control register 8 (IP8) ............................................................... 15-29
(9)
Interrupt priority control register 9 (IP9) ............................................................... 15-30
Chapter 16
Bus Port Functions
16.1 Overview.......................................................................................................................... 16-1
16.2 Port Operation .................................................................................................................. 16-1
16.2.1
Port Operation When Accessing Program Memory................................................. 16-1
16.2.2
Port Operation When Accessing Data Memory ....................................................... 16-2
16.3 External Memory Access ................................................................................................. 16-3