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Semiconductor
ML 670100
/ 27
5
PIN DESCRIPTIONS (Cont.)
Type
Bus
control
signals nBACK
Signal Name I/O Direction Description
nBREQ
Input
This input is a bus request signal from an external device.
It represents a secondary function for I/O port PIO7[6].
This output is an acknowledgment signal to a bus request signal
from an external device. It represents a secondary function for
I/O port PIO7[7].
This input is an external fast interrupt request (FIQ). When
accepted, the request is processed as an FIQ exception.
This inputs are external interrupt requests. They represent
secondary functions for I/O port PIO3[7:0].
These pins function as capture trigger input pins for Flexible
Timer channels 5-0 in capture mode. They represent secondary
functions for I/O port PIO4[5:0].
These pins function as output pins for Flexible Timer channels
5-0 in compare output or PWM mode. They represent
secondary functions for I/O port PIO4[5:0].
These pins function as Flexible Timer channels 1 and 0 clock
input pins. They represent secondary functions for I/O port
PIO4[7:6].
This output is the transmit data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[7].
This input is the receive data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[6].
This output is the transmit data for the Clock Synchronous
Serial Interface 0. It represents a secondary function for I/O
port PIO5[2].
This input is the receive data for the Clock Synchronous Serial
Interface 0. It represents a secondary function for I/O port
PIO5[1].
Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 0. It represents a secondary
function for I/O port PIO5[0].
Output
This output is the transmit data for the Clock Synchronous
Serial Interface 1. It represents a secondary function for I/O
port PIO5[5].
Input
This input is the receive data for the Clock Synchronous Serial
Interface 1. It represents a secondary function for I/O port
PIO5[4].
Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 1. It represents a secondary
function for I/O port PIO5[3].
Output
Interru-
pts
nEFIQ
Input
nEIR[7:0]
Input
Timers TMIN[5:0]
Input
TMOUT[5:0] Output
TMCLK[1:0] Input
Serial
ports
ASI_TXD
Output
ASI_RXD
Input
CSI0_TXD
Output
CSI0_RXD
Input
CSI0_SCLK
CSI1_TXD
CSI1_RXD
CSI1_SCLK