
Semiconductor
ML9041
37/54
10) Busy Flag/Address Counter Read (Execution time: 1
m
s)
The “BF” bit (DB7) of this instruction tells whether the ML9041 is busy in internal operation (BF
= “1”) or not (BF = “0”).
When the “BF” bit is “1”, the ML9041 cannot accept any other instructions. Before inputting a
new instruction, check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9041 outputs the correct value of the address counter. The value
of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the
DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding
address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may
have been incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
A character code (P
7
to P
0
) is read from the DDRAM, Display–ON data (P
7
to P
0
) from the
ABRAM or a character pattern (P
7
to P
0
) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the
Transfer Mode Setting instruction (see 3).
Note:
Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read
instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see
5) is input before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read
data is correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note:
The execution time of this instruction is 37
m
s at an oscillation frequency (OSC) of 270
kHz.
RS
1
1
RS
0
0
R/
W
1
DB
7
BF
DB
6
O
6
DB
5
O
5
DB
4
O
4
DB
3
O
3
DB
2
O
2
DB
1
O
1
DB
0
O
0
Instruction code:
RS
1
1
RS
0
1
R/
W
1
DB
7
P
7
DB
6
P
6
DB
5
P
5
DB
4
P
4
DB
3
P
3
DB
2
P
2
DB
1
P
1
DB
0
P
0
Instruction code: