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參數(shù)資料
| 型號： | MM54C374J/883B |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | CMOS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 190K |
| 代理商： | MM54C374J/883B |
AC Electrical Characteristics
MM54C373MM74C373 TA e 25 C CL e 50 pF tr e tf e 20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0 tpd1
Propagation Delay
VCC e 5V CL e 50 pF
165
330
ns
LATCH ENABLE to Output
VCC e 10V CL e 50 pF
70
140
ns
VCC e 5V CL e 150 pF
195
390
ns
VCC e 10V CL e 150 pF
85
170
ns
tpd0 tpd1
Propagation Delay Data
LATCH ENABLE e VCC
In to Output
VCC e 5V CL e 50 pF
155
310
ns
VCC e 10V CL e 50 pF
70
140
ns
VCC e 5V CL e 150 pF
185
370
ns
VCC e 10V CL e 150 pF
85
170
ns
tSET-UP
Minimum Set-Up Time Data In
tHOLD e 0ns
to CLOCKLATCH ENABLE
VCC e 5V
70
140
ns
VCC e 10V
35
70
ns
fMAX
Maximum LATCH ENABLE
Frequency
VCC e 5V
35
67
MHz
VCC e 10V
45
90
MHz
tPWH
Minimum LATCH ENABLE
VCC 5V
75
150
ns
Pulse Width
VCC e 10V
55
110
ns
tr tf
Maximum LATCH ENABLE
VCC e 5V
NA
m
s
Rise and Fall Time
VCC e 10V
NA
m
s
t1H t0H
Propagation Delay OUTPUT
RL e 10k CL e 5pF
DISABLE to High Impedance
VCC e 5V
105
210
ns
State (from a Logic Level)
VCC e 10V
60
120
ns
tH1 tH0
Propagation Delay OUTPUT
RL e 10k CL e 50 pF
DISABLE to Logic Level
VCC e 5V
105
210
ns
(from High Impedance State)
VCC e 10V
45
90
ns
tTHL tTLH
Transition Time
VCC e 5V CL e 50 pF
65
130
ns
VCC e 10V CL e 50 pF
35
70
ns
VCC e 5V CL e 150 pF
110
220
ns
VCC e 10V CL e 150 pF
70
140
ns
CLE
Input Capacitance
LE Input (Note 2)
75
10
pF
COD
Input Capacitance
OUTPUT DISABLE
75
10
pF
Input (Note 2)
CIN
Input Capacitance
Any Other Input (Note 2)
5
75
pF
COUT
Output Capacitance
High Impedance
10
15
pF
State (Note 2)
CPD
Power Dissipation Capacitance
Per Package (Note 3)
200
pF
AC Parameters are guaranteed by DC correlated testing
3
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