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參數(shù)資料
| 型號(hào)： | MM74C89 |
| 廠(chǎng)商： | Fairchild Semiconductor Corporation |
| 英文描述： | 64-Bit 3-STATE Random Access Read/Write Memory |
| 中文描述： | 64位三態(tài)隨機(jī)存取讀/寫(xiě)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 60K |
| 代理商： | MM74C89 |
www.fairchildsemi.com
4
M
AC Electrical Characteristics
(Note 2)
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise noted
Symbol
Parameter
Note 2:
AC Parameters are guaranteed by DC correlated testing.
Note 3:
Capacitance is guaranteed by periodic testing.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note,
AN-90.
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay from
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, t
WS
=
0
V
CC
=
10V, t
WS
=
0
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, C
L
=
5 pF, R
L
=
10k
V
CC
=
10V, C
L
=
5 pF, R
L
=
10k
270
500
ns
Memory Enable
Access Time from
Address Input
100
350
130
220
650
280
ns
ns
ns
t
ACC
t
SA
Address Setup Time
150
60
60
ns
ns
ns
t
HA
Address Hold Time
40
400
150
ns
ns
ns
t
ME
Memory Enable Pulse Width
250
90
t
SR
Write Enable Setup
Time for a Read
Write Enable Setup
0
0
ns
ns
ns
t
WS
t
ME
t
ME
Time for a Write
Write Enable Pulse Width
ns
ns
ns
t
WE
300
100
160
60
t
HD
Data Input Hold Time
50
25
50
ns
ns
ns
t
SD
Data Input Setup
25
ns
ns
ns
t
1H
, t
0H
Propagation Delay from a Logical
“1” or Logical “0” to the High
180
85
300
120
Impedance State from
Memory Enable
Propagation Delay from a Logical
t
1H
, t
0H
V
CC
=
50V, C
L
=
5 pF, R
L
=
10k
V
CC
=
10V, C
L
=
5 pF, R
L
=
10k
180
300
ns
“1” or Logical “0” to the High
Impedance State from
Write Enable
85
120
ns
C
IN
C
OUT
C
PD
Input Capacity
Output Capacity
Power Dissipation Capacity
Any Input (Note 3)
Any Output (Note 3)
(Note 4)
5
pF
pF
pF
6.5
230
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