參數(shù)資料
型號(hào): MM908E621ACDWB
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror
中文描述: 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡
文件頁(yè)數(shù): 15/62頁(yè)
文件大?。?/td> 540K
代理商: MM908E621ACDWB
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
908E621
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
°
C
T
J
125
°
C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate
(25)
,
(26)
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
50
μ
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
50
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
50
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
50
μ
s
Duty Cycle 1: D1 = t
Bus_rec(min)
/ (2 x t
BIT
), t
BIT
= 50
μ
s, V
SUP
= 7.0V..18V
D1
0.396
Duty Cycle 2: D2 = t
Bus_rec(max)
/ (2 x t
BIT
), t
BIT
= 50
μ
s, V
SUP
= 7.6V..18V
Driver Characteristics for Slow Slew Rate
(25)
,
(27)
D2
0.581
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
100
μ
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
100
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
100
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
100
μ
s
Duty Cycle 3: D3 = t
Bus_rec(min)
/ (2 x t
BIT
), t
BIT
= 96
μ
s, V
SUP
= 7.0V..18V
D3
0.417
Duty Cycle4: D4 = t
Bus_rec(max)
/ (2 x t
BIT
), t
BIT
= 96
μ
s, V
SUP
= 7.6V..18V
D4
0.590
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SR
FAST
20
V/
μ
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay
(28)
t
RL
3.5
6.0
μ
s
Receiver Recessive Propagation Delay
(28)
t
RH
3.5
6.0
μ
s
Receiver Propagation Delay Symmetry
t
R-SYM
-2.0
2.0
μ
s
Bus Wake-Up Deglitcher
t
PROPWL
30
50
150
μ
s
Bus Wake-Up Event Reported
(29)
t
WAKE
20
μ
s
Notes
25.
V
SUP
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k
, 6.8 nF/660
, 10 nF/500
. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
See
Figure 6
, page
18
.
See
Figure 7
, page
19
.
Measured between LIN signal threshold V
IL
or V
IH
and 50% of RXD signal.
t
WAKE
is typically 2 internal clock cycles after LIN rising edge detected. See
Figure 9
and
Figure 8
, page
19
. In Sleep mode the V
DD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
26.
27.
28.
29.
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