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參數(shù)資料
| 型號： | MM908E626R2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 中文描述： | 集成的步進(jìn)電機(jī)驅(qū)動器，帶有嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | MM908E626R2 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E626
17
LVF
—
Low-Voltage Flag Bit
This read/write flag is set on a low-voltage condition. Clear
LVF by writing a logic [1] to LVF. If a low-voltage condition is still
present while writing a logic [1] to LVF, the writing has no effect.
Therefore, a low-voltage interrupt cannot be lost due to
inadvertent clearing of LVF. Reset clears the LVF bit. Writing a
logic [0] to LVF has no effect.
1 = Low-voltage condition has occurred.
0 = Low-voltage condition has not occurred.
HVF
—
High-Voltage Flag Bit
This read/write flag is set on a high-voltage condition. Clear
HVF by writing a logic [1] to HVF. If high-voltage condition is still
present while writing a logic [1] to HVF, the writing has no effect.
Therefore, a high-voltage interrupt cannot be lost due to
inadvertent clearing of HVF. Reset clears the HVF bit. Writing a
logic [0] to HVF has no effect.
1 = High-voltage condition has occurred.
0 = High-voltage condition has not occurred.
OCF
—
Overcurrent Flag Bit
This read-only flag is set on an
overcurrent condition. Reset
clears the OCF bit. To clear this flag, write a logic [1] to the
appropriate overcurrent flag in the SYSSTAT Register. See
Figure 6
, which shows the
two
signals triggering the OCF.
1 = High-current condition has occurred.
0 = High-current condition has not occurred.
Figure 6. Principal Implementation for OCF
Interrupt Mask Register (IMR)
LINIE
—
LIN Line Interrupt Enable Bit
This read/write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
1 = Interrupt requests from LINF flag enabled.
0 = Interrupt requests from LINF flag disabled.
HTIE
—
High-Temperature Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high-
temperature flag, HTF. Reset clears the HTIE bit.
1 = Interrupt requests from HTF flag enabled.
0 = Interrupt requests from HTF flag disabled.
LVIE
—
Low-Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the low-
voltage flag, LVF. Reset clears the LVIE bit.
1 = Interrupt requests from LVF flag enabled.
0 = Interrupt requests from LVF flag disabled.
HVIE
—
High-Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high-
voltage flag, HVF. Reset clears the HVIE bit.
1 = Interrupt requests from HVF flag enabled.
0 = Interrupt requests from HVF flag disabled.
OCIE
—
Overcurrent Interrupt Enable Bit
This read/write bit enables CPU interrupts by the overcurrent
flag, OCF. Reset clears the OCIE bit.
1 = Interrupt requests from OCF flag enabled.
0 = Interrupt requests from OCF flag disabled.
OCF
HVDD_OCF
HB_OCF
Register Name and Address: IMR - $04
Bit7
6
5
4
3
2
1
Bit0
Read
0
0
LINIE
HTIE
LVIE
HVIE
OCIE
0
Write
Reset
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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