參數(shù)資料
型號(hào): MM912G634CM1AER2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 107/349頁(yè)
文件大?。?/td> 0K
描述: IC 48KS12 LIN2XLS/HS ISENSE
標(biāo)準(zhǔn)包裝: 2,000
應(yīng)用: 自動(dòng)
核心處理器: HCS12
程序存儲(chǔ)器類型: 閃存(48 kB)
控制器系列: HCS12
RAM 容量: 2K x 8
接口: LIN
電源電壓: 5.5 V ~ 27 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
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MM912_634 Advance Information, Rev. 10.0
Freescale Semiconductor
195
pin low, in order to allow the negative edge to be detected by the target.In this case, the target will not execute the SYNC protocol
but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when
there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The
worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target
the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the
accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not
a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge,
after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference for the reader
to better understand the BDM internal behavior. It is not recommended that this procedure
be used in a real application.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider
the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length.
Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See
Figure 60 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after
the command is aborted a new command could be issued by the host computer.
Figure 60. ACK Abort Procedure at the Command Level
NOTE
Figure 60 does not represent the signals in a true timing scale
Figure 61 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is
connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a
pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued
along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse.
Since this is not a probable situation, the protocol does not prevent this conflict from happening.
READ_BYTE
READ_STATUS
BKGD Pin
Memory Address
New BDM Command
Host
Target
Host
Target
Host
Target
SYNC Response
From the Target
(Out of Scale)
BDM Decode
and Starts to Execute
the READ_BYTE Command
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
相關(guān)PDF資料
PDF描述
345-026-540-802 CARDEDGE 26POS DUAL .100 GREEN
345-026-540-801 CARDEDGE 26POS DUAL .100 GREEN
AYF534465 CONN SOCKET FPC 0.5MM 44POS SMD
345-026-540-204 CARDEDGE 26POS DUAL .100 GREEN
MM912G634CM1AE IC 48KS12 LIN2XLS/HS ISENSE
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