參數(shù)資料
型號(hào): MM912G634CM1AER2
廠商: Freescale Semiconductor
文件頁數(shù): 99/349頁
文件大小: 0K
描述: IC 48KS12 LIN2XLS/HS ISENSE
標(biāo)準(zhǔn)包裝: 2,000
應(yīng)用: 自動(dòng)
核心處理器: HCS12
程序存儲(chǔ)器類型: 閃存(48 kB)
控制器系列: HCS12
RAM 容量: 2K x 8
接口: LIN
電源電壓: 5.5 V ~ 27 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
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MM912_634 Advance Information, Rev. 10.0
Freescale Semiconductor
188
NOTE
If an attempt is made to activate BDM before being enabled, the CPU resumes normal
instruction execution after a brief delay. If BDM is not enabled, any hardware
BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x3_FF00 to 0x3_FFFF.
BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses these registers which are readable anytime by
the BDM. However, these registers are not readable by user programs.
When BDM is activated while CPU executes code overlapping with BDM firmware space the saved program counter (PC) will be
auto incremented by one from the BDM firmware, no matter what caused the entry into BDM active mode (BGND instruction,
BACKGROUND command or breakpoints). In such a case the PC must be set to the next valid address via a WRITE_PC
command before executing the GO command.
5.31.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode.
Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for
execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for
a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within
128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the
operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation
requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM
hardware commands are listed in Table 267.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the
system memory map but share addresses with the application in memory. To distinguish between physical memory locations that
share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows
the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
Table 267. Hardware Commands
Command
Opcode
(hex)
Data
Description
BACKGROUND
90
None
Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the part
enters active background mode.
ACK_ENABLE
D5
None
Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE
D6
None
Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE
E4
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
READ_BD_WORD
EC
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
READ_BYTE
E0
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
READ_WORD
E8
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map. Must be aligned
access.
WRITE_BD_BYTE
C4
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD
CC
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map. Must be aligned access.
WRITE_BYTE
C0
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
WRITE_WORD
C8
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map. Must be aligned
access.
Note:
179. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete
for all BDM WRITE commands.
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