參數(shù)資料
型號: MM912G634CV1AE
廠商: Freescale Semiconductor
文件頁數(shù): 109/349頁
文件大?。?/td> 0K
描述: IC 48KS12 LIN2XLS/HS ISENSE
標準包裝: 250
應(yīng)用: 自動
核心處理器: HCS12
程序存儲器類型: 閃存(48 kB)
控制器系列: HCS12
RAM 容量: 2K x 8
接口: LIN
電源電壓: 5.5 V ~ 27 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP 裸露焊盤
包裝: 托盤
供應(yīng)商設(shè)備封裝: 48-LQFP 裸露焊盤(7x7)
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MM912_634 Advance Information, Rev. 10.0
Freescale Semiconductor
197
5.31.4.9
SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication
speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC
command, the host should perform the following steps:
1.
Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency
2.
Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host
clock.)
3.
Remove all drive to the BKGD pin so it reverts to high impedance.
4.
Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1.
Discards any incomplete command received or bit retrieved.
2.
Waits for BKGD to return to a logic one.
3.
Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4.
Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5.
Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6.
Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target
speed and the communication protocol can easily tolerate speed errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is
referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider
the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular
SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target
synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse
will not be issued.
5.31.4.10
Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is
active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed.
This facilitates stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is
executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt
service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but peripherals are free
running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer
exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address
pointing to BDM firmware address space.
When tracing through user code which contains stop instructions the following will happen when the stop instruction is traced:
The CPU enters stop mode and the TRACE1 command can not be finished before leaving the low power mode. This is
the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM
hardware commands except the BACKGROUND command are operational after tracing a stop instruction and still being
in stop mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational.
As soon as stop mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the
corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded
when tracing a stop instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1
command after CPU exited from stop mode. All valid commands sent during CPU being in stop mode or after CPU
exited from stop mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode
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