參數(shù)資料
型號(hào): MM912G634CV1AER2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 109/349頁(yè)
文件大小: 0K
描述: IC 48KS12 LIN2XLS/HS ISENSE
標(biāo)準(zhǔn)包裝: 2,000
應(yīng)用: 自動(dòng)
核心處理器: HCS12
程序存儲(chǔ)器類型: 閃存(48 kB)
控制器系列: HCS12
RAM 容量: 2K x 8
接口: LIN
電源電壓: 5.5 V ~ 27 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP 裸露焊盤
包裝: 帶卷 (TR)
供應(yīng)商設(shè)備封裝: 48-LQFP 裸露焊盤(7x7)
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)當(dāng)前第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)第325頁(yè)第326頁(yè)第327頁(yè)第328頁(yè)第329頁(yè)第330頁(yè)第331頁(yè)第332頁(yè)第333頁(yè)第334頁(yè)第335頁(yè)第336頁(yè)第337頁(yè)第338頁(yè)第339頁(yè)第340頁(yè)第341頁(yè)第342頁(yè)第343頁(yè)第344頁(yè)第345頁(yè)第346頁(yè)第347頁(yè)第348頁(yè)第349頁(yè)
MM912_634 Advance Information, Rev. 10.0
Freescale Semiconductor
197
5.31.4.9
SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication
speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC
command, the host should perform the following steps:
1.
Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency
2.
Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host
clock.)
3.
Remove all drive to the BKGD pin so it reverts to high impedance.
4.
Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1.
Discards any incomplete command received or bit retrieved.
2.
Waits for BKGD to return to a logic one.
3.
Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4.
Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5.
Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6.
Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target
speed and the communication protocol can easily tolerate speed errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is
referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider
the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular
SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target
synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse
will not be issued.
5.31.4.10
Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is
active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed.
This facilitates stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is
executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt
service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but peripherals are free
running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer
exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address
pointing to BDM firmware address space.
When tracing through user code which contains stop instructions the following will happen when the stop instruction is traced:
The CPU enters stop mode and the TRACE1 command can not be finished before leaving the low power mode. This is
the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM
hardware commands except the BACKGROUND command are operational after tracing a stop instruction and still being
in stop mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational.
As soon as stop mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the
corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded
when tracing a stop instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1
command after CPU exited from stop mode. All valid commands sent during CPU being in stop mode or after CPU
exited from stop mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode
相關(guān)PDF資料
PDF描述
345-026-527-204 CARDEDGE 26POS DUAL .100 GREEN
345-026-527-202 CARDEDGE 26POS DUAL .100 GREEN
345-026-527-201 CARDEDGE 26POS DUAL .100 GREEN
345-026-524-804 CARDEDGE 26POS DUAL .100 GREEN
345-026-524-802 CARDEDGE 26POS DUAL .100 GREEN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MM912G634CV2AP 功能描述:馬達(dá)/運(yùn)動(dòng)/點(diǎn)火控制器和驅(qū)動(dòng)器 48KS12 LIN2xLS/HS Isense RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube
MM912G634CV2APR2 制造商:Freescale Semiconductor 功能描述:Relay Driver 48-Pin LQFP T/R 制造商:Freescale Semiconductor 功能描述:48KS12 LIN2XLS/HS ISENSE - Tape and Reel 制造商:Freescale Semiconductor 功能描述:IC MCU 16BIT 48KB FLASH 48LQFP 制造商:Freescale Semiconductor 功能描述:48KS12 LIN2xLS/HS Isense
MM912G634DM1AE 功能描述:馬達(dá)/運(yùn)動(dòng)/點(diǎn)火控制器和驅(qū)動(dòng)器 48KS12 LIN2xLS/HS Isense RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube
MM912G634DM1AER2 功能描述:馬達(dá)/運(yùn)動(dòng)/點(diǎn)火控制器和驅(qū)動(dòng)器 48KS12 LIN2xLS/HS Isense RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube
MM912G634DV1AE 功能描述:16位微控制器 - MCU 48KS12 LIN2XLS/HS ISENSE RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT