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參數(shù)資料
| 型號： | MP7612 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| 中文描述： | 八通道12位DAC陣列的D / A轉(zhuǎn)換器與放大器輸出和串行數(shù)據(jù)/地址，以控制邏輯 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 231K |
| 代理商： | MP7612 |
MP7612
9
Rev. 3.00
Table 2. MP7612
Ideal DAC Output vs. Input Code
Hex Code
Output Voltage = 2
Vr (–1 +
(Vr = +5 V)
0 0 0
10
(–1 + 0) = –10
7 F F
10
(–1 + ) = –4.88 mV
4096
Binary Code
2
D
4096
)
000000000000
011111111111
100000000000
4096
8 0 0
10
(–1 + ) = 0
100000000001
4096
8 0 1
10
(–1 + ) = 4.88 mV
111111111111
4096
F F F
10
(–1 + ) = 9.99512
Note: See Electrical Characteristics for real system accuracy
SERIAL INTERFACE DIAGRAMS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MP7612AP | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612AS | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612BP | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612BS | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7613 | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MP7612AP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612AS | 制造商:EXAR 制造商全稱:EXAR 功能描述:Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612BP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7612BS | 制造商:EXAR 制造商全稱:EXAR 功能描述:Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic |
| MP7613 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic |
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