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參數(shù)資料
| 型號(hào)： | MP8775AQ |
| 廠商： | MICRO POWER SYSTEMS |
| 元件分類： | ADC |
| 英文描述： | CMOS 20 MSPS, 8-Bit, High Speed Analog-to-Digital Converter |
| 中文描述： | 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 511K |
| 代理商： | MP8775AQ |
MP8775
5
Rev. 3.01
N + 1
N
N--1
Output
Codes
Analog
Input
Code Width (N) = V
(
N+1)
-- V
(
N)
LSB = [
V
RT
-- V
RB
] / 256
DNL
(N)
= [ V
(N+1)
-- V
(N)
] -- LSB
Figure 2. DNL Measurement
LSB
DNL
7
6
5
4
3
2
1
Output
Codes
Analog Input (Volt)
Figure 3. INL Error Calculation
Best Fit Line
EFS
EZS
LSB
Ideal Transfer Line
Real Transfer Line
INL
V
(N+1)
V
(N)
Figure 4. Equivalent Input Circuit
V
RT
+ V
RB
2
CLK
CLK
CLK
5pF
1.5pF
CLK
CLK
CLK
5pF
1.5pF
V
IN
[N--2]
AV
DD
V
IN
6 pF
Figure 5. Typical Circuit Connections
50
Analog
Input
0.1
μ
F
0.1
μ
F
0.1
μ
F
+5 V
Clock
V
IN
V
DD
V
RTS
V
RT
V
RB
V
RBS
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLK
MP8775
10
μ
F
Digital
Outputs
AGND
APPLICATION NOTES
Signals should not exceed AV
DD
+0.5V or go below AGND
--0.5V or DV
DD
+0.5 V or DGND --0.5 V. All pins have internal
protection diodes that will protect them from short transients
(<100
μ
s) outside the supply range.
AGND and DGND pins are connected internally through the
P-- substrate. DC voltage differences between these pins will
cause undesirable internal substrate currents.
The power supply (AV
DD
) and reference voltage (V
RT
&V
RB
)
pins should be decoupled with 0.1
μ
F and 10
μ
F capacitors to
AGND, placed as close to the chip as possible.
The digital outputs should not drive long wires or buses. The
capacitive coupling and reflections will contribute noise to the
conversion.
It is possible for the data valid delay (t
DL
) to be equal to or
greater than the high pulse width of the sampling clock (t
PWH
),
See
Figure 1.
This can cause timing related errors. Forsample
rates above 14 MSPS use only the rising edge of the sample
clock (CLK) to latch data from the MP8775 to other parts of the
system.
The reference can be biased internally by shorting V
RT
to
V
RTS
andV
RB
toV
RBS
. Thiswillgenerate0.6VatV
RB
and2.6V
at V
RT
(see
Figure 5.).
If the internal reference pins V
RTS
and/or V
RBS
are not used
they should be left unconnected.
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