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參數(shù)資料
| 型號： | MPC2106SG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 128K X 72 CACHE SRAM MODULE, 9 ns, PDMA182 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MPC2106SG66 |
MPC2105A
MPC2106A
MPC2105B
MPC2106B
14
MOTOROLA FAST SRAM
TAG RAM MATCH CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
Clock High Write to MATCH Invalid
tKHML
—
7
ns
Clock High Read to MATCH Valid
tKHMV
—
10
ns
Address Valid to MATCH Valid
tAVMV
—
10
ns
MATCH Valid Hold from Address Change
tAXMX
2
—
ns
TG Low to MATCH Invalid
tGLML
—
7
ns
TG High to MATCH Valid
tGHMX
—
8
ns
TAG RAM RESET (TCLR) CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
TCLR Setup Time
tSTC
4
—
ns
TCLR Hold Time
tHTC
1
—
ns
Status Bit Reset Time
tSRST
—
60
ns
Status Bit Hold from TCLR Low
tSHRS
2
—
ns
TCLR Low to MATCH Invalid
tRSML
—
10
ns
TCLR High to MATCH Valid
tRSMV
—
100
ns
TCLR Low to TAG High–Z
tRSQZ
—
10
ns
TCLR High to TAG Active
tRSQX
—
100
ns
STANDBY Setup to TCLR Low
tPDSR
30
—
ns
TCLR High to TWE Low
tRHWX
80
—
ns
OUTPUT
Z0 = 50
50
VL = 1.5 V
(a)
(b)
5 pF
+5 V
OUTPUT
255
480
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. Test Loads
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