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參數(shù)資料
| 型號： | MPC5553MVR132 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 61/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 1.5MB FLASH 132MHZ 416-PBGA |
| 標(biāo)準(zhǔn)包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 132MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 220 |
| 程序存儲器容量： | 1.5MB（1.5M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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MPC5553 Microcontroller Data Sheet, Rev. 4
Revision History for the MPC5553 Data Sheet
Freescale Semiconductor
64
Table 7 (Pin Status for Fast Pads During the Power Sequence) Power Sequence Pin Status for Fast Pads
Changed title to Pin Status for Fast Pads During the Power Sequence
Changed preceding paragraph
From:
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current
spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting POR, the
pads are in a high impedance state (Hi-Z).
To:
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies
are powered.
Table 8 (Pin Status for Medium and Slow Pads During the Power Sequence) Power Sequence Pin Status for Medium/Slow Pads:
Changed title to Pin Status for Medium and Slow Pads During the Power Sequence
Updated preceding paragraph.
Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications:
Spelled the slash ‘/’ as ‘a(chǎn)nd’ as well as ‘I/O’ as ‘input/output.’ Still very confusing. Deleted ‘input/output’.
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if EBTS = 0; VDDE2 and VDDE3 have
a range of 1.6–3.6 V if EBTS =1.
Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (IOH_S = –2.0 mA):’
Created a left-justified second line and moved ‘IOH_S = –2.0 mA’ from the 1st line to the second line and deleted
the parentheses. Created a left-justified third line that reads ‘IOH_S = –1.0 mA.’
Spec 20, column 4, Min.: Added a blank line before and after ‘0.80
V
DDEH’ and put ‘0.85 VDDEH’ on the last
line.
Spec 22, column 2,’Slow and medium output low voltage (IOL_S = 2.0 mA):’ Created a left-justified second line
and moved ‘IOL_S = 2.0 mA.’ from the 1st line to the second line and deleted the parentheses. Created a
left-justified third line that reads ‘IOL_S = 1.0 mA.’ Column 5, Max: Added a blank line before and after ‘0.20
VDDEH’ and put ‘0.15 VDDEH’ on the last line.
Spec 26: Changed ‘AN[12]_MA[1]_SDO’ to ‘AN[13]_MA[1]_SDO’.
Spec 27a: Operating current 1.5 V supplies @ 132 MHz changed to:
1.65 typical = 460
1.35 typical = 360
1.65 high = 510
1.35 high = 410
Spec 27b, Operating current 1.5 V supplies @ 114 MHz changed to:
1.65 typical = 410
1.35 typical = 310
1.65 high = 460
1.35 high = 370
Spec 27c, Operating current 1.5 V supplies @ 82 MHz changed to:
1.65 typical = 330
1.35 typical = 225
1.65 high = 385
1.35 high = 290
Spec 28: Changed 132 MHz to fMAX MHz.
Footnote 3 changed to read: If standby operation is not required, connect VSTBY to ground.
Footnote 6 is now: Figure 3 (Power-Up Sequence (VRC33 Grounded))shows an illustration of the IDD_STBY
values interpolated for these temperature values.
Deleted footnote 9: ‘Preliminary. Final specification pending characterization.’
Deleted duplicate footnote: ‘Absolute value of current, measured at VIL and VIH.
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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