參數(shù)資料
型號(hào): MPC5561MZQ132R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PBGA324
封裝: 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, TEPBGA-324
文件頁(yè)數(shù): 49/56頁(yè)
文件大?。?/td> 1044K
代理商: MPC5561MZQ132R
Revision History for the MPC5561 Data Sheet
MPC5561 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
53
5.2
Information Changed Between Revisions 1.0 and 2.0
The following table lists the changes made throughout the document.
Table 22 Bus Operation Timing:
Changed Spec 1 for the minimum 67 MHz column from: 15.2 to 14.9.
Specs 5 and 6: corrected format to show the bus timing values for various frequencies with EBTS bit = 0 and
EBTS bit = 1.
Table 23 External Interrupt Timing:
Footnote 1: Deleted ‘fSYS = 132 MHz’, ‘.VDD33 and VDDSYN = 3.0–3.6 V’ and ‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24 eTPU Timing, Figure 16 eTPU Timing and Figure 17 eTPU Input/Output Timing: Deleted – No eTPU in MPC5561.
Table 24 eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Deleted ‘. . .fSYS = 132 MHz. . .’, ‘. . .VDD33 and VDDSYN = 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF
with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 16 eMIOS Timing Added figure.
Table 25 DSPI Timing:
Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad
type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’
Footnote 1: Deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 26 EQADC SSI Timing Characteristics:
Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
Spec 1: FCK frequency -- removed.
Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 to Spec 2.
Footnote 1, deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6V.’
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
Figure 27 MPC5561 324 Package:
Changed ball label T21 from VRCVSS to PLLCFG2.
Deleted the version number and date.
Table 29. Information Changed Between Rev. 1.0 and Rev. 2.0
Location
Description of Changes
Section 1, “Overview”: Added new 11th paragraph about FlexRay. Removed discussion in the SIU and DSPI paragraphs about
deserialization and serialization, and chaining. Removed reference to SIU_DISR register.
Table 6 VCR/POR Electrical Specifications:
Added to Specs 1, 2 and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5 negate
(internal POR). RESET must remain asserted until the power supplies are within the operating conditions as
specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall
outside the operating conditions and until the internal POR asserts.
Table 28. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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