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參數(shù)資料
| 型號： | MPC5566MZP144 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 61/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 3MB FLASH 416PBGA |
| 標準包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 144MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 256 |
| 程序存儲器容量： | 3MB（3M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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MPC5566 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5566 Data Sheet
Freescale Semiconductor
64
Table 22, Bus Operation Timing:
Added a column to the table for 72 MHz minimum and maximum bus frequencies.
Spec 1: 72 MHz Min. column = 13.3.
Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Specs 5, and 6: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
CAL_CS[0:3], CAL_DATA[0:15], CAL_OE, CAL_RD_WR, CAL_TS, CAL_WE/BE[0:1].
Spec 5: EBI and Calibration sections, 72 MHz Min column, EBTS = 0 is 1.0, EBTS = 1 is 1.5.
Spec 6: EBI section, 72 MHz Max column, EBTS = 0 is 5.0, EBTS = 1 is 6.0.
Spec 6a: Calibration section, 72 MHz Max column, EBTS = 0 is 6.0, EBTS = 1 is 7.0
Specs 7 and 8: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
CAL_DATA[0:15], CAL_RD_WR, CAL_TS.
Table 23, External Interrupt Timing:
Footnote 1: Deleted ‘. . FSYS = 132 MHz’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘ .and CL = 200 pF with SRC =
0b11.’
Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24, eTPU Timing
Footnote 1: Deleted ‘. . .FSYS = 132 MHz’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘a(chǎn)nd CL = 200 pF with
SRC = 0b11.’
Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 25, eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Deleted ‘. . .FSYS = 132 MHz, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and ‘a(chǎn)nd CL = 200 pF with
SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17, eMIOS Timing: Added figure.
Table 26, DSPI Timing:
Added 144 MHz column to the table.
Spec1:SCK Cycle Time: changes to values: 80 MHz, min. = 24.4; 112 MHz, min. = 17.5, max = 2.1;
132 MHz, min. = 14.8, max = 1.8; 144 MHz, min. = 13.6, max = 1.6.
Spec1:SCK Cycle Time: Added footnote 4 to the 144 MHz min. and max values that reads: Preliminary.
Specification pending final characterization
Spec 2, PCS to SCK delay, 144 MHz, min. TBD
Spec 3, After SCK delay, 144 MHz, min. TBD
Spec 9, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
Spec 10, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
Spec 11, Master (MTFE = 1, CPHA = 0), 144 MHz, max TBD
Spec 12, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad
type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’
Footnote 1: Deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location
Description of Changes
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