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參數(shù)資料
| 型號： | MPC5566MZP144 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 3MB FLASH 416PBGA |
| 標準包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 144MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 256 |
| 程序存儲器容量： | 3MB（3M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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Electrical Characteristics
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
17
41
VSSSYN to VSS differential voltage
VSSSYN – VSS
–50
50
mV
42
VRCVSS to VSS differential voltage
VRCVSS – VSS
–50
50
mV
43
VDDF to VDD differential voltage
VDDF – VDD
–100
100
mV
43a VRC33 to VDDSYN differential voltage
VRC33 – VDDSYN
–0.1
0.1 19
V
44
Analog input differential signal range (with common mode 2.5 V)
VIDIFF
–2.5
2.5
V
45
Operating temperature range, ambient (packaged)
TA = (TL to TH)TL
TH
C
46
Slew rate on power-supply pins
—
50
V/ms
1 VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6–3.6 V if
SIU_ECCR[EBTS] = 1.
2 | VDDA0 – VDDA1 | must be < 0.1 V.
3 VPP can drop to 3.0 V during read operations.
5 Applies to CLKOUT, external bus pins, and Nexus pins.
6 Maximum average RMS DC current.
7 Eight-way cache enabled (L1CSR0[CORG] = 0b0).
8 Average current measured on automotive benchmark.
9 Peak currents can be higher on specialized code.
10 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents are possible if an ‘idle’ loop that crosses cache lines is run from cache. Write code to avoid this
condition.
11 Four-way cache enabled (L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,
L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).
12 The current specification relates to average standby operation after SRAM has been loaded with data. For power up current see
13 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.
14 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
15 Absolute value of current, measured at VIL and VIH.
16 Weak pullup/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
17 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC
to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
18 VSSA refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
19 Up to 0.6 V during power up and power down.
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec
Characteristic
Symbol
Min
Max.
Unit
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