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| 型號： | MPC5602PEFMLL |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 21/72頁 |
| 文件大小： | 661K |
| 代理商： | MPC5602PEFMLL |
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MPC560xP Datasheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
28
3.3
Thermal Characteristics
VDD_LV_CORx
SR
Internal supply voltage
—
V
VSS_LV_CORx
SR
Internal reference voltage
—
0
V
VDD_LV_PLL
3,4,5
SR
Internal supply voltage
—
V
VSS_LV_PLL
SR
Internal reference voltage
—
0
V
TA
SR
Ambient temperature under bias
fCPU = 64 MHz
-40
105
°C
TJ
SR
Junction temperature under bias
—
-40
150
°C
1 Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2 The power supply voltage must be identical for ADC0 and ADC1. As long as that condition is met, ADC0 and ADC1 can
be operated at 5 V with the rest of the device operating at 3.3 V.
3 To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted
to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external
ballast emitter.
4 The low voltage supplies (V
DD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the
low voltage supply to the data flash module. The integrity of the connections are monitored by an on-chip supply
and ground comparator. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted and monitored.
VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
VDD_LV_PLL and VSS_LV_PLL are independent of other supplies.
5 Low voltage supply/ground lines of the FMPLLs internally are physically separate but are shorted with a double-bonding
connection on the VDD_LV_PLL and VSS_LV_PLL pins.
Table 8. Thermal Characteristics for 144-pin LQFP1
1 Thermal characteristics are targets based on simulation that are subject to change per device characterization.
No.
Symbol
Parameter
Conditions
Value Unit
1RθJA
CC Thermal resistance junction-to-ambient
natural convection2
2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Single layer board - 1s
43
°C/W
2RθJMA CC Thermal resistance junction-to-ambient
natural convection2
Four layer board - 2s2p
35
°C/W
3RθJA
CC Thermal resistance junction-to-ambient2
@ 200 ft./min.3, single layer board
3 Flow rate of forced air flow.
34
°C/W
@ 200 ft./min.3, four layer board 2s2p
29
°C/W
5RθJB
CC Thermal resistance junction to board4
22
°C/W
6RθJC
CC Thermal resistance junction to case5
8°C/W
7
Ψ
JT
CC Junction to package top natural convection6
2°C/W
Table 7. Recommended Operating Conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Min
Max1
Unit
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