MPC560xP Datasheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
7
Figure 3. LQFP 100-pin Configuration (top view)1
2.2
Pin Descriptions
The following sections provide signal descriptions and related information about the functionality and configuration of the
MPC560xP devices.
1. Availability of port pin alternate functions depends on product selection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NMI
dspi1 SCK/A[6]
flexray0 CA RX/etimer1 ETC[2]/ctu0 EXT TRG/D[1]
dspi1 SOUT/A[7]
sscm DEBUG[4]/dspi0 CS0/flexpwm0 X[1]/C[4]
dspi1 SIN/A[8]
sscm DEBUG[5]/dspi0 SCK/flexpwm0 FAULT[3]/C[5]
dspi1 CS0/etimer1 ETC[5]/dspi0 CS7/A[5]
sscm DEBUG[7]/dspi0 SIN/flexpwm0 A[1]/C[7]
dspi0 CS1/etimer1 ETC[4]/lin1 TXD/C[3]
VSS_LV_COR0
VDD_LV_COR0
VDD_HV_IO1
VSS_HV_IO1
flexpwm0 X[0]/lin1 TXD/D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET_B
dspi1 CS2/flexpwm0 FAULT[3]/dspi0 CS5/D[8]
dspi0 CS3/fcu0 F[0]/dspi3 SOUT/D[5]
dspi0 CS2/dspi3 SCK/flexpwm0 FAULT[1]/D[6]
VSS_LV_PLL
VDD_LV_PLL
A[4]/etimer1 ETC[0]/dspi2 CS1/etimer0 ETC[4]
VPP TEST
D[14]/flexpwm0 B[1]/dspi3 CS3/dspi3 SIN
C[14]/etimer1 ETC[2]/ctu0 EXT TGR
C[13]/etimer1 ETC[1]/ctu0 EXT IN/flexpwm0 ext. sync
D[12]/flexpwm0 X[1]/lin1 RXD
VDD_HV_FL
VSS_HV_FL
D[13]/flexpwm0 A[1]/dspi3 CS2/dspi3 SOUT
VSS_LV_COR1
VDD_LV_COR1
A[3]/etimer0 ETC[3]/dspi2 CS0/flexpwm0 B[3]
VDD_HV_IO2
VSS_HV_IO2
B[4]/jtag0 TDO
jtag0 TCK
jtag0 TMS
B[5]/jtag0 TDI
A[2]/etimer0 ETC[2]/dspi2 SIN/flexpwm0 A[3]
C[12]/etimer0 ETC[5]/dspi2 CS3/dspi3 CS1
C[11]/etimer0 ETC[4]/dspi2 CS2/dspi3 CS0
D[11]/flexpwm0 B[0]/dspi3 CS1/dspi3 SCK
D[10]/flexpwm0 A[0]/dspi3 CS0
A[1]/etimer0 ETC[1]/dspi2 SOUT/fcu0 F[1]/sscm DEBUG[7]
A[0]/etimer0 ETC[0]/dspi2 SCK/fcu0 F[0]
dspi
1
CS
3
/fc
u
0
F[
1
]/
ds
pi3
SIN/
dspi
0
CS
4
/D[
7]
ad
c
0
A
N
[4
]/
E[
1]
adc0
A
N
[2
]/
C[
1]
adc
0
AN[
0]/
lin0
RXD/
B[
7]
adc0
A
N
[3
]/
C[
2]
adc0
A
N
[1
]/
et
im
er
0
ET
C[
5
]/
B[
8]
ad
c
0
A
N
[5
]/
E[
2]
V
DD_HV_
A
D0
V
SS_HV_
A
D0
ad
c
0
-a
d
c
1
AN[
11]
/B[
9]
ad
c0-ad
c
1
AN[
12]/
B[1
0
]
ad
c0-ad
c
1
AN[
13]/
B[1
1
]
ad
c0-ad
c
1
AN[
14]/
B[1
2
]
V
DD_HV_
A
D1
V
SS_HV_
A
D1
ad
c
1
AN[
4]/
D[1
5
]
adc1
AN[0
]/
lin1
RXD
/B[1
3
]
ad
c
1
AN[
2]/
B[1
5
]
adc1
A
N
[1
]/
et
0
ETC[
4]/
B[1
4
]
adc1
A
N
[3
]/
C[
0]
ad
c
1
A
N
[5
]/
E[
0]
BCTRL
V
DD
_L
V_
REGCOR
V
SS
_L
V_
REGCOR
V
DD_HV
_REG
A[
15]
/saf
e
ty
por
t0
RXD
/et
imer
1
ETC[
5]
A[
14]
/saf
e
ty
por
t0
TXD/
et
im
er
1
ETC[
4]
C[
6]
/dspi
0
SO
UT/
fl
e
x
pwm
0
B[
1
]/
ss
cm
DEB
UG
[6
]
D[
2]
/fl
e
x
ra
y
0
CB
RX/
et
imer
1
ETC[
3]
/fl
e
x
p
w
m
0
X[3]
B[
6]
/C
LK
OUT/
dspi
2
CS2
A[
13]
/dspi
2
SIN/
fl
e
x
pwm
0
B[
2]/
fl
e
x
p
w
m
0
F
A
U
LT[0]
A[
9]
/dspi
2
CS1/
fl
e
x
pw
m
0
F
A
UL
T[0]
/fl
e
x
pwm
0
B[
3]
V
SS
_L
V_
COR2
V
DD
_L
V_
COR2
C[
8]
/dspi
1
CS1/
fl
e
x
pw
m
0
F
A
UL
T[2]
/dspi
0
CS6
D[
4]
/fl
e
x
ra
y
0
CB
TR
EN/
eti
m
er1
ETC[5]
/fl
e
x
pwm
0
B[
3]
D[
3]
/fl
e
x
ra
y
0
CB
TX/
et
im
er
1
ETC
[4]
/fl
e
x
pw
m
0
A[3]
V
SS
_HV_I
O
3
V
DD
_HV_I
O
3
D[
0]
/fl
e
x
ra
y
0
CA
TX/
et
im
er
1
ETC
[1]
/fl
e
x
pw
m
0
B[1]
C[
15]
/fl
e
x
ra
y
0
CA
TR
EN/
eti
m
er1
ETC[0
]/
fl
e
x
pwm
0
A[
1]/
ct
u0
EXT
IN/
fl
e
x
pwm
0
e
x
t.
s
y
nc
C[
9]
/dspi
2
CS3/
fl
e
x
pw
m
0
F
A
UL
T[2]
/fl
e
x
pwm
0
X[
3]
A[
12]
/dspi
2
SO
UT/
fl
e
x
p
w
m
0
A[2]
/fle
x
p
w
m
0
B[2
]
A[
11]
/dspi
2
SCK/
fl
e
x
p
w
m
0
A[0]
/fle
x
p
w
m
0
A[
2]
A[
10]
/dspi
2
CS0/
fl
e
x
p
w
m
0
B[0]
/fl
e
x
pwm
0
X[
2]
B[
3]
/l
in0
RXD/
s
scm
DEB
UG[3]
B[
2]
/li
n
0
TXD/
s
scm
DEB
UG[2]
C[
10]
/dspi
2
CS2/
fl
e
x
p
w
m
0
FA
U
LT
[1
]/
fl
e
x
pwm
0
A[
3]
B[
1]
/can0
RXD/
et
im
er
1
ETC
[3]
/ss
cm
DEB
UG
[1
]
B[
0]
/can0
TXD/
et
im
er
1
ETC[2]
/s
scm
DEB
UG[0]
LQFP 100