參數(shù)資料
型號(hào)： MPC5602PEFMLQ
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
文件頁(yè)數(shù)： 46/72頁(yè)
文件大?。?/td> 661K
代理商： MPC5602PEFMLQ
MPC560xP Datasheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
50
3.16.2
RESET_B Pin Characteristics
Table 30 gives the RESET_B pin characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V]=0) operation.
Table 31 gives the RESET_B pin characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V]=1) operation.
Table 30. RESET_B Pin1 Characteristics (5.0 V, NVUSRO[PAD3V5V]=0)
1 The RESET_B pin is weak pull-up during reset.
No.
Symbol
Parameter
Conditions
Min Max
Unit
1WFRST
SR RESET pulse is sure to be filtered2
2 Pulse in between 70 ns and 500 ns may be either filtered or provided.
VDD=VDD_LV_CORx
—40
ns
2WNFRST SR RESET pulse is sure not to be filtered
VDD=VDD_LV_CORx 500
—
ns
3tPLH
CC
A
C
i
nput
Propagation delay on rising edge
Input slope = 15 ns 0.8
7
ns
Input slope = 5 ns
0.8
7
Input slope = 2 ns
0.6
7
4tPHL
CC
Propagation delay on falling edge
Input slope = 15 ns 0.8
7
ns
Input slope = 5 ns
0.8
7
Input slope = 2 ns
0.6
7
5fmax
TBD
Frequency of operation
Input slope = 15 ns
—
25
MHz
Input slope = 5 ns
—
50
Input slope = 2 ns
—
100
6tDC
TBD
Duty cycle
40
60
%
7tpd
CC
A
C
outpu
t
Propagation delay from VDD_HV_IOx/2 of internal
signal to Nchannel switch on condition
Load = 25 pF
1
15
ns
Load = 50 pF
1
15
8
TBD
CC
Slope at falling edge
Load = 25 pF
1
8
ns
Load = 50 pF
2
15
9
ΔI
tr
CC
Current slew rate at rising edge of current
Load = 25 pF
3
50
mA/ns
Load = 50 pF
3
50
Table 31. RESET_B Pin1 Characteristics (3.3 V, INVUSRO[PAD3V5V]=1)
No.
Symbol
Parameter
Conditions
Min Max
Unit
1WFRST
SR RESET pulse is sure to be filtered
—
40
ns
2WNFRST SR RESET pulse is sure not to be filtered
500
—
ns
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