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| 型號(hào)： | MPC5606SCLQ6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144 |
| 文件頁(yè)數(shù)： | 126/136頁(yè) |
| 文件大小： | 858K |
| 代理商： | MPC5606SCLQ6 |
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
9
Additional notes on low power operation:
Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low
power modes
The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected
as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external
oscillator delay
MPC5606S devices include an internal voltage regulator that includes the following features:
— Regulates input to generate all internal supplies
— Manages power gating
— Low power regulators support operation when in STOP and STANDBY modes to minimize power consumption
— Startup on-chip regulators in <50
s for rapid exit of STOP and STANDBY modes
— Low voltage detection on main supply and 1.2 V regulated supplies
1.6.2
e200z0h core processor
The e200z0h processor is similar to other processors in the e200zx series but supports only the VLE instruction set and does
not include the signal processing extension for DSP applications or a floating point unit.
The e200z0h has all the features of the e200z0 plus:
Branch acceleration using Branch Target Buffer (BTB)
Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory
via independent Instruction and Data BIUs
The e200z0h processor uses a four stage in-order pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction
Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback
(stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a
Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 8
32
Hardware Multiplier array, result feed-forward hardware, and a hardware divider.
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions.
A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated
Branch Address adder to minimize delays during change of flow operations. Branch target prefetching from the BTB is
performed to accelerate certain taken branches. Sequential prefetching is performed to ensure a supply of instructions into the
execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into
an instruction buffer capable of holding four instructions.
Conditional branches not taken execute in a single clock. Branches with successful target prefetching have an effective
execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension
of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective
single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The
5 A high level summary of some key durations that need to be considered when recovering from low power modes.
This does not account for all durations at wake up. Other delays will be necessary to consider including, but not
limited to the external supply start-up time.
IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.
All other wake-up times must be added to determine the total start-up time
6 This is the startup of the regulator that happens after the 5 V has reached beyond its POR range. If the external
supply ramp rate is slow, measure from when VREG has crossed beyond the POR threshold, otherwise this value
will depend on the ramp rate of the external supply (VDDR).
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相關(guān)代理商/技術(shù)參數(shù) |
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| MPC5606S-DEMO-V2 | 功能描述:開發(fā)板和工具包 - 其他處理器 EVB MPC5606S RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC5607B | 制造商:Freescale Semiconductor 功能描述: |
| MPC5607B_13 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MicrocontrollerData Sheet |
| MPC5607BECLLR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5607BECLQR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
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