參數(shù)資料
型號(hào)： MPC5606SVLQ6R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 85/136頁
文件大小： 858K
代理商： MPC5606SVLQ6R
MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
52
2.9.1
Signal details
Table 10. Signal details
Signal
Peripheral
Description
ABS[0]
BAM
Alternate Boot Select. Gives an option to boot by downloading code
via CAN or LIN.
ANS[0:15]
ADC
Inputs used to bring into the device sensor-based signals for A/D
conversion. ANS[0:15] connect to ATD channels [32:47].
MA[0:2]
ADC
These three control bits are output to enable the selection for an
external Analog Mux for expansion channels. The available 8
multiplexed channels connect to ATD channels [64:71].
FABM
Force Alternate Boot mode. Forces the device to boot from the
external bus (Can or LIN). If not asserted, the device boots up from
the lowest flash sector containing a valid boot signature.
DCU_DE
DCU
Indicates that valid pixels are present.
DCU_HSYNC
DCU
Horizontal sync pulse for TFT-LCD display
DCU_PCLK
DCU
Output pixel clock for TFT-LCD display
DCU_R[0:7],
DCU_G[0:7],
DCU_B[0:7]
DCU
Red, green and blue color 8-bit Pixel values for TFT-LCD displays
DCU_TAG
DCU
Indicates when a tagged pixel is present in safety mode
DCU_VSYNC
DCU
Vertical sync pulse for TFT-LCD display
PCS[0..2]_0,
PCS[0..2]_1
DSPI
Peripheral chip selects when device is in Master mode; not used in
slave modes.
SCK_0,
SCK_1
DSPI
SPI clock signal—bidirectional
SIN_0,
SIN_1
DSPI
SPI data input signal
SOUT_0,
SOUT_1
DSPI
SPI data output signal
PCS0_2
QuadSPI
Peripheral chip select for serial flash mode or chip select 0 for SPI
master mode
IO2/PCS1_2
QuadSPI
Chip select 1 for SPI master mode and bidirectional IO2 for serial
flash mode
IO3/PCS2_2
QuadSPI
Chip select 2 for SPI master mode and bidirectional IO3 for serial
flash mode
IO0/SIN_2
QuadSPI
Data input signal for SPI master and slave modes and bidirectional
IO0 for serial flash mode
IO1/SOUT_2
QuadSPI
Data output signal for SPI master and slave modes and bidirectional
IO1 for serial flash mode
SCK_2
QuadSPI
Clock output signal for SPI master and serial flash modes and clock
input signal for SPI slave mode
eMIOSA[8:23],
eMIOSB[16:23]
eMIOS
Enhanced Modular Input Output System. 16+8 channel eMIOS for
timed input or output functions.
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