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| 型號(hào)： | MPC5606SVMG6R |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MAPBGA-208 |
| 文件頁(yè)數(shù)： | 123/134頁(yè) |
| 文件大?。?/td> | 890K |
| 代理商： | MPC5606SVMG6R |
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Electrical characteristics
MPC560xS Microcontroller Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
89
3.13
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 43. Slow external crystal oscillator (32 KHz) electrical characteristics
Symbol
C
Parameter
Conditions1
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified
Value2
2 All values need to be confirmed during device characterization.
Unit
Min
Typ
Max
fSXOSC
SR T Slow external crystal oscillator
frequency
—
32
—
40
kHz
VSXOSC
CC T Oscillation amplitude
VDD = 3.3 V ± 10%
1.12
1.33
1.74
V
TVDD = 5.0 V ± 10%
1.12
1.37
1.74
ISXOSC
CC D Slow external crystal oscillator
consumption
——
—
5
A
TSXOSCSU CC T Slow external crystal oscillator
start-up time
——
—
23
3 The quoted figure is based on a board that is properly laid out and has no stray capacitances.
s
VIH
SR D Input high level CMOS Schmitt
Trigger
Oscillator bypass mode
0.65VDD
—VDD + 0.4
V
VIL
SR D Input low level CMOS Schmitt
Trigger
Oscillator bypass mode
0.4
—
0.35VDD
V
Table 44. FMPLL electrical characteristics
Symbol
C
Parameter
Conditions1
1 V
DDPLL = 1.2 V ± 10%, TA = 40 to 105 °C, unless otherwise specified.
Value2
2 All values need to be confirmed during device characterization.
Unit
Min
Typ
Max
fPLLIN
SR T FMPLL reference clock3
3 PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
—4
—
64
MHz
PLLIN
SR T FMPLL reference clock duty cycle3 —40
—
60
%
fPLLOUT CC T FMPLL output clock frequency
—
16
—
64
MHz
fCPU
CC T System clock frequency
—
644
4 f
CPU 64 MHz can be achieved only at temperatures up to 105 °C with a maximum FM depth of 2%.
MHz
tLOCK
CC T FMPLL lock time
Stable oscillator (fPLLIN = 16 MHz)
—
200
s
t
PKJIT
CC T FMPLL jitter (peak to peak)
fPLLIN = 16 MHz (resonator)
—
500
ps
t
LTJIT
CC T FMPLL long term jitter
fPLLIN = 16 MHz (resonator)
—
1.5
ns
IPLL
CC D FMPLL consumption
TA = 25 °C
—
4
mA
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC5606S
products
in
208
MAPBGA
packages
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