
MPC561/MPC563 Reference Manual, Rev. 1.2
Index-2
Freescale Semiconductor
Branch
Branch latch control (BLC)
19-12Branch processing unit
3-4branch target buffer
4-14Breakpoint
asserted flag (BKPT)
19-14Breakpoint counter A value and control register
23-45Breakpoint counter B value and control register
23-46burst indicator (BURST),
9-37burst read cycle (illustration),
9-21burst write cycle (illustration),
9-26Bus
off interrupt
bus exception control cycles,
9-45bus interface
bus operation
address transfer phase related signals,
9-37basic transfer protocol,
9-8bus exception control cycles,
9-45single beat transfer
single beat read flow,
9-9single beat transfer,
9-9storage reservation,
9-42termination signals,
9-40bus transfer signals,
9-1bus signals (illustration),
9-3receive message buffer code
16-5C
cache control instructions,
3-43CALRAM
CAN2.0B
Channel
assignments
conditions latch (CCL)
19-13interrupt
enable
/disable field (CH)
19-15request level (CIRL)
19-15register breakpoint flag (CHBK)
19-14