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參數(shù)資料
| 型號(hào)： | MPC565MZP56R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 1M FLASH 56MHZ 388-PBGA |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 56MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器容量： | 1MB（1M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 36K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 帶卷 (TR) |
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MOTOROLA
MPC565/MPC566 Product Brief
5
Detailed Feature List
1.2.10 Debug Features
Extensive system debug support
On-chip watchpoints and breakpoints
Program flow tracking
Background debug mode (BDM)
1.2.10.1 Nexus Debug Port (Class 3)
Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)
Nine- or 16-pin interface
1.2.10.2 Message Data Link Controller (DLCMD2) Module
Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment
register
SAE J1850 Class B data communications network interface compatible and ISO compatible for
low-speed (
<125 Kbps) serial data communications in automotive applications
10.4 Kbps variable pulse width (VPW) bit format
Digital noise filter, collision detection
Hardware cyclical redundancy check (CRC) generation and checking
Block mode receive and transmit supported
4x receive mode supported (41.6 Kbps)
Digital loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
Dedicated register for symbol timing adjustments
Inter-module bus 3 (IMB3) slave interface
Power-saving IMB3 stop mode with automatic wakeup on network activity
Power-saving IMB3 CLOCKDIS mode
Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit
Polling and IMB3 interrupt generation with vector lookup available
1.2.11 Integrated I/O System
True 5-V I/O
1.2.11.1 Time Processor Units (TPU3)
Three time processing units (TPU3)
— 16 channels each
Each TPU3 is a microcoded timer subsystem
One 6-Kbyte and one 4-Kbyte dual-port TPU RAM (DPTRAM), one (6-Kbyte) shared by two
TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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