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參數(shù)資料
| 型號(hào)： | MPC565MZP56R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 1M FLASH 56MHZ 388-PBGA |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 56MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器容量： | 1MB（1M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 36K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 帶卷 (TR) |
10
MPC565/MPC566 Product Brief
MOTOROLA
Additional MPC565 Differences
CALRAM causes DSI exception only if the data relocation (DR) bit in the core machine state
register, MSR[DR], is set.
— L2U on MPC555 already followed this protocol, but the LRAM did not. Now all L-bus
peripherals follow this protocol.
— The MSR[DR] bit is described in the reference manual for more information.
Four additional PRDS control bits were added to the USIU to allow more granularity of PRDS
control on a part
BBC includes a 4-Kbyte DECRAM that can be used if compression is not used or is not available.
3
SRAM Keep-Alive Power Behavior
The SRAM has three keep-alive power pins (VDDSRAM1, VDDSRAM2, and VDDSRAM3). These pins
provide keep-alive power to the SRAM arrays in the CALRAM modules and the DPTRAM modules.
The VDDSRAM1 pin powers the 32-Kbyte CALRAM A during keep-alive while power is off to the
MPC565 (except for the keep-alive power supplies). CALRAM A keeps all of its 32 Kbytes powered during
power down.
The VDDSRAM2 pin powers the 4-Kbyte CALRAM B module. The VDDSRAM3 pin powers the
DPTRAM modules during keep-alive as well as during normal operation. The CALRAM modules only
power their arrays from the VDDSRAM pins during keep-alive. During normal operation, they are powered
by the normal internal VDD of the part.
The DPTRAM modules (6 Kbytes and 4 Kbytes) and the 4-Kbyte DECRAM in the BBC module power their
arrays via the VDDSRAM3 pin during keep-alive and are supplied by VDD during normal operation.
4
MPC565 Memory Map
The internal memory map is organized as a single 4-Mbyte block. This is shown in Figure 3. This block can
be moved to one of eight different locations. The internal memory space is divided into the following
sections:
Flash memory (1 Mbyte) — U-bus memory
Static RAM memory (36 Kbytes CALRAM) — L-bus memory
Control registers and IMB3 modules (64 Kbytes), partitioned as
— USIU and flash control registers
— UIMB interface and IMB3 modules
— CALRAM and READI control registers (L-bus control register space)
The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. These eight
locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000, as shown in
Figure 2. There is a user programmable register in the USIU to configure the internal memory map to one
of the eight possible locations. Programmability of internal memory map location allows multiple chip
system.
The IMB3 address space block in Figure 3 shows memory allocation for IMB3 modules. It does not show
the actual memory space required for individual modules. All modules are mapped to the low address,
numerically, of the memory allocated for that module in the IMB3 address space.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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