參數(shù)資料
型號: MPC5668GF0AVMGR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208
封裝: 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO151AAF-1, MAPBGA-208
文件頁數(shù): 54/66頁
文件大?。?/td> 889K
代理商: MPC5668GF0AVMGR
MPC5668x Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
58
Figure 26. MII Receive Signal Timing Diagram
4.14.8.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 27. MII Transmit Signal Timing Diagram
Table 34. MII Transmit Signal Timing1
1 Output pads configured with SRC = 0b11.
Spec
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
ns
M6
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
25
ns
M7
TX_CLK pulse width high
35%
65%
TX_CLK period
M8
TX_CLK pulse width low
35%
65%
TX_CLK period
M1
M2
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M3
M4
M6
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M7
M8
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC5668x
products
in
208
and
256
MAPBGA
packages
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