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MOTOROLA
Chapter 10. Memory Controller
10-25
Write and Byte Enable Signals
NOTE
The LBDIP/TBDIP function can operate only when the cycle
termination is internal, using the number of wait states
programmed in one of the ORx registers. The LBDIP/TBDIP
function cannot be activated at the same time—results are
unknown.
10.4 Write and Byte Enable Signals
The GPCM determines the timing and value of the WE/BE signals if allowed by the port
size of the accessed bank, the transfer size of the transaction and the address accessed.
The functionality of the WE/BE[0:3] pins depends upon the value of the write enable/byte
select (WEBS) bit in the corresponding BR register. Setting WEBS to 1 will enable these
pins as BE, while clearing it to zero will enable them as WE.WE is asserted only during
write access, while BE is asserted for both read and write accesses. The timing of the
WE/BE pins remains the same in either case, and is determined by the TRLX, ACS and
CSNT bits.
The upper WE/BE (WE[0]/BE[0]) indicates that the upper eight bits of the data bus
(D0–D7) contains valid data during a write/read cycle. The upper-middle write byte enable
(WE[1]/BE[1]) indicates that the upper-middle eight bits of the data bus (D8–D15) contains
valid data during a write/read cycle. The lower-middle write byte enable (WE[2]/BE[2])
indicates that the lower-middle eight bits of the data bus (D16–D23) contains valid data
during a write/read cycle. The lower write/read enable (WE[3]/BE[3]) indicates that the
lower eight bits of the data bus contains valid data during a write cycle.
The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a
16-bit port (PS = 10) and a 8-bit port (PS = 01) are shown in
Table 10-3. This table shows
which write enables are asserted (indicated with an ‘X’) for different combinations of port
size and transfer size