參數(shù)資料
型號(hào)： MPC603AFE80CC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 80 MHz, RISC PROCESSOR, CQFP240
封裝： 32 X 32 MM, 3.10 MM HEIGHT, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240
文件頁(yè)數(shù)： 29/31頁(yè)
文件大?。?/td> 153K
代理商： MPC603AFE80CC
603 Hardware Specifications
7
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 603. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specications” and tested for
conformance to the AC specications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. PLL_CFG signals should be set
prior to power up and not altered afterwards. These specications are for 66 MHz core frequency with
33 MHz bus (66C—2:1 bus mode), 66 MHz bus (66A—1:1 bus mode), and 80 MHz core frequency with
40 MHz bus (80C—2:1 bus mode). Parts are sold by maximum processor core frequency and bus mode; see
Section 1.9, “Ordering Information.”
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1.
Table 6. Clock AC Timing Specifications
Vdd = 3.3
± 5% V dc, GND = 0 V dc, 0 ≤ T
j ≤ 105 °C
Num
Characteristic
66C
66A
80C
Unit
Notes
Min
Max
Min
Max
Min
Max
Processor frequency
16.67
66.0
16.67
66.0
16.67
80.0
MHz
1
VCO frequency
120
240
120
240
120
240
MHz
SYSCLK (bus) frequency
16.67
33.0
16.67
66.0
16.67
40.0
MHz
1
SYSCLK cycle time
40.0
60.0
30.0
60.0
25.0
60.0
ns
2,3
SYSCLK rise and fall time
—
2.0
—
2.0
—
2.0
ns
2
4
SYSCLK duty cycle measured at 1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4
603 internal PLL-relock time
—
100
—
100
—
100
s
3, 5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8,
“System Design Information,” for valid PLL_CFG[0–3] settings, and to Section 1.9, “Ordering Information,” for
available frequencies and part numbers.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum
of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
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相關(guān)PDF資料
PDF描述
MPC603AFE66AC 32-BIT, 66.67 MHz, RISC PROCESSOR, CQFP240
MPC603AFE80CC RISC PROCESSOR, CQFP240
MPC603AFE66CC RISC PROCESSOR, CQFP240
MPC603AIP200E 32-BIT, 200 MHz, RISC PROCESSOR, CPGA288
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