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參數(shù)資料
| 型號： | MPC603AFE80CC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | 32 X 32 MM, 3.10 MM HEIGHT, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 153K |
| 代理商： | MPC603AFE80CC |
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8
603 Hardware Specifications
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
1.4.2.2 Input AC Specications
Table 7 provides the input AC timing specications for the 603 as dened in Figure 2 and Figure 3.
Table 7. Input AC Timing Specifications
Vdd = 3.3
± 5% V dc, GND = 0 V dc, 0 ≤ T
j ≤ 105 °C
Num
Characteristic
66C
66A
80C
Unit
Notes
Min
Max
Min
Max
Min
Max
10a
Address/data/transfer attribute inputs valid to
SYSCLK (input setup)
4.0
—
2.5
—
3.5
—
ns
2
10b
All other inputs valid to SYSCLK (input setup)
6.0
—
4.5
—
5.5
—
ns
3
10c
Mode select inputs valid to HRESET (input
setup) (for DRTRY, QACK and TLBISYNC)
8 *
tsysclk
—
8 *
tsysclk
—
8 *
tsysclk
—
ns
4, 5, 6
11a
SYSCLK to address/data/transfer attribute
inputs invalid (input hold)
1.0
—
1.0
—
1.0
—
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
—
1.0
—
1.0
—
ns
3
11c
HRESET to mode select inputs invalid (input
hold) (for DRTRY, QACK, and TLBISYNC)
0—0—0—
ns
4, 6
Notes:
1. All input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the
rising edge of the input SYSCLK. Both input and output timings are measured at the pin (see Figure 2).
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],
TC[0–1], TBST, TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, XATS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). This specication is for
conguration-mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
s) during the power-on reset sequence.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
6. These values are guaranteed by design, and are not tested.
VM
CVil
CVih
SYSCLK
2
3
1
4
VM = Midpoint Voltage (1.4 V)
4
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.
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