- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1955 > MPC603RVG300LC (Freescale Semiconductor)MPU RISC PID7V-603E 255FCCBGA PDF資料下載
參數(shù)資料
| 型號： | MPC603RVG300LC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 30/31頁 |
| 文件大小： | 0K |
| 描述： | MPU RISC PID7V-603E 255FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC6xx |
| 處理器類型： | 32-位 MPC603e PowerPC |
| 速度： | 300MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BCBGA 裸露焊盤，255-FCCBGA |
| 供應(yīng)商設(shè)備封裝： | 255-FCCBGA（21x21） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁
PID7t-603e Hardware Specifications, Rev. 5
8
Freescale Semiconductor
Electrical and Thermal Characteristics
This figure provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
4.2.2
Input AC Specifications
This table provides the input AC timing specifications for the PID7t-603e as defined in Figure 2 and
SYSCLK jitter
—
±150
—
±150
—
±150
—
±150
ps
4
PID7t internal PLL-relock time
—
100
—
100
—
100
—
100
s3, 5
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0–3] signal description in Section 8, “System Design Information,” for valid
PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under
±150 ps to guarantee the input/output timing of Section 4.2.2, “Input AC Specifications,” and Section 4.2.3, “Output AC
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required
for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. This specification
also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must
be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
6. Operation below 150 MHz is supported only by PLL_CFG[0–3] = 0b0101. Refer to Section 8.1, “PLL Configuration” for
additional information.
Table 7. Clock AC Timing Specifications (continued)
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 °C
Num
Characteristic
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8266AVVPJDC | IC MPU POWERQUICC II 480-TBGA |
| MPC8272ZQTMFA | IC MPU POWERQUICC II 516-PBGA |
| MPC8306CVMADDCA | IC PROCESSOR E300 369MAPBGA |
| MPC8308VMAFF | IC PROCESSOR E300 473MAPBGA |
| MPC8309CVMAFDCA | IC PROCESSOR E300 489MAPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC603RZT200LC | 功能描述:微處理器 - MPU 603E 255PBGA RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC604E | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PowerPC 604e-TM RISC Microprocessor Technical Summary |
| MPC6071 | 制造商:International Rectifier 功能描述: |
| MPC616 | 制造商:Hammond Manufacturing 功能描述:6" X 16" MAGNET PANEL COVER |
| MPC-628-011B | 制造商:FCI 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。