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參數(shù)資料
| 型號： | MPC7410THX500LE |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FCBGA-360 |
| 文件頁數(shù)： | 6/73頁 |
| 文件大?。?/td> | 929K |
| 代理商： | MPC7410THX500LE |
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14
MPC7410 RISC Microprocessor Hardware Specications
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
Table 7. Clock AC Timing Specications
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
350
400
350
450
350
500
MHz
1
VCO frequency
fVCO
700
800
700
900
700
1000
MHz
1
SYSCLK frequency
fSYSCLK
33
133
33
133
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
30
7.5
30
7.5
30
ns
SYSCLK rise and fall time
tKR and tKF
—
0.5
—
0.5
—
0.5
ns/V
2
SYSCLK duty cycle
measured at OVDD/2
tKHKL/tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4
Internal PLL-relock time
—
100
—
100
—
100
s5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 1.8.1, “PLL Conguration,”
for valid PLL_CFG[0:3] settings.
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a
result, the 0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the
3.3-V bus interface. Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from
0.2 to 1.2 V) in 0.5 ns for the 1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change
(from 0.4 to 2.4 V) in 1 ns.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
specication also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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| MPC7410VS450LE | 功能描述:微處理器 - MPU NITRO R1.4 105C PB FREE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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