參數(shù)資料
型號(hào)： MPC8241TZQ166D
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357
封裝： 25 X 25 MM, 2.52 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-357
文件頁(yè)數(shù)： 19/58頁(yè)
文件大?。?/td> 853K
代理商： MPC8241TZQ166D
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
26
Freescale Semiconductor
Electrical and Thermal Characteristics
4.6.2
I2C AC Electrical Specifications
Table 13 provides the AC timing parameters for the I2C interfaces.
Pulse width of spikes which must be suppressed by
the input filter
tI2KHKL
050
ns
2
Input current each I/O pin (input voltage is between
0.1
× OVDD and 0.9 × OVDD(max)
II
–10
10
μA3
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the MPC8245 Integrated Processor Reference Manual for information on the digital filter used.
3. I/O pins obstruct the SDA and SCL lines if the OVDD is switched off.
Table 13. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 12).
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
4
1.3
—
μs
High period of the SCL clock
tI2CH
4
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
4
0.6
—
μs
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
4
0.6
—
μs
Data setup time
tI2DVKH
4
100
—
ns
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0 2
—
μs
Data output delay time:
tI2OVKL
—0.93
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Table 12. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
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