參數(shù)資料
型號: MPC8245LZU266B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù): 14/64頁
文件大?。?/td> 940K
代理商: MPC8245LZU266B
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
21
Electrical and Thermal Characteristics
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
11a
VM = midpoint voltage (1.4 V).
Memory
10b-d
Inputs/Outputs
13b
14b
VM
SDRAM_SYNC_IN
Input Timing
Output Timing
12b-d
2.0 V
0.8 V
2.0 V
Tos
11a = input hold time of SDRAM_SYNC_IN to memory.
12b-d = SDRAM_SYNC_IN to output valid timing.
13b = output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
Tos = offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
sys_logic_clk
VM
PCI_SYNC_IN
VM
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to be seen
before sys_logic_clk once the DLL locks, if no other accommodation is made for the delay.
(After DLL Locks
Shown in 2:1 Mode
Notes:
10b-d = input signals valid timing.
if no compensation
for Tos is made)
OVDD ÷ 2
10a
11c
PCI_SYNC_IN
PCI
12a
13a
14a
OVDD ÷ 2
0.4
× OVDD
0.615
× OVDD
0.285
× OVDD
Input Timing
Output Timing
Inputs/Outputs
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