參數(shù)資料
型號(hào)： MPC8245LZU266B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁(yè)數(shù)： 43/64頁(yè)
文件大小： 940K
代理商： MPC8245LZU266B
48
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
System Design Information
There is no standardized way to number the COP header shown in Figure 28; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 28 is common to all known emulators.
Figure 28. COP Connector Diagram
HRESET
HRST_CPU
HRST_CTRL
From Target
Board Sources
HRESET
13
SRESET 5
NC
11
VDD_SENSE
6
5 2
15 3
1 k
10 k
10 k
10 k
OVDD
CHKSTOP_IN 6
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
He
a
d
e
r
14 4
Key
Notes:
1. QACK is an output on the MPC8245 and is not required at the COP header for emulation.
2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8245.
Connect pin 5 of the COP header to OVDD with a 1- k pull-up resistor.
3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8245.
Connect pin 15 of the COP header to OVDD with a 10-k pull-up resistor.
4. Pin 14 is not physically present on the COP header.
QACK 1
OVDD
10 k
OVDD
TRST
10 k
OVDD
10 k
10 k
5. SRESET functions as output SDMA12 in extended ROM mode.
6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
MPC8245
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
1
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