參數(shù)資料
型號(hào)： MPC8266AZUPIBX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 33/111頁(yè)
文件大?。?/td> 1007K
代理商： MPC8266AZUPIBX
28
MPC826xA (HiP4) Family Hardware Specications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Conguration Modes
1010_010
66/33 MHz
4/8
266 MHz
3.5
300 MHz
3
88 MHz
1010_011
66/33 MHz
4/8
266 MHz
4
350 MHz
3
88 MHz
1010_100
66/33 MHz
4/8
266 MHz
4.5
400 MHz
3
88 MHz
1011_000
66/33 MHz
4/8
266 MHz
2
212MHz
2.5
106 MHz
1011_001
66/33 MHz
4/8
266 MHz
2.5
265 MHz
2.5
106 MHz
1011_010
66/33 MHz
4/8
266 MHz
3
318 MHz
2.5
106 MHz
1011_011
66/33 MHz
4/8
266 MHz
3.5
371 MHz
2.5
106 MHz
1011_100
66/33 MHz
4/8
266 MHz
4
424 MHz
2.5
106 MHz
1100_0007
66/33MHz
2/4
133MHz
Bypass
66MHz
2
66 MHz
1100_0017
66/33MHz
3/6
200MHz
Bypass
80MHz
2.5
80 MHz
1100_0107
66/33MHz
3/6
200MHz
Bypass
66MHz
3
66 MHz
1 The user should verify that all buses and functions run frequencies that are within the supported ranges.
2 The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency
is divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2.
3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so
that the resulting conguration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are
possible (note that the three input clock frequencies are only three of many possible input clock
frequencies):
1. 50 MHz input clock, MODCK_H–MODCK_L[0110–011] (with a core multiplication factor of 4, a CPM
multiplication factor of 4, and a bus division factor of 3), and PCI_MODCK = 0 (see note 2 above). The
PCI frequency is 50 MHz and the resulting conguration equals the part’s maximum possible frequencies
of 266 MHz CPU, 200 MHz CPM, and 66 MHz 60x bus.
2. 66 MHz input clock, MODCK_H–MODCK_L[0100–001], and PCI_MODCK = 1 (see note 2 above) to
achieve a PCI frequency of 33 MHz and a conguration of 200MHz CPU, 200 MHz CPM, and 66 MHz
60x bus.
3. 40 MHz input clock, MODCK_H–MODCK_L[1001–011], and PCI_MODCK = 0 (see note 2 above) to
achieve a PCI frequency of 40 MHz and a conguration of 160 MHz CPU, 160 MHz CPM, and 40 MHz
60x bus.
Note that with each of the examples, any one of several values for MODCK_H–MODCK_L could possibly
be used as long as the resulting conguration does not exceed the part’s rating.
4 Core frequency = (60x bus frequency)(core multiplication factor)
5 Bus frequency = CPM frequency / bus division factor
6 In this mode, PCI_MODCK must be “1”.
7 In this mode the Core PLL is bypassed (core frequency equals bus frequency; for debug purpose only).
Table 19. Clock Conguration Modes in PCI Agent Mode (Continued)1
MODCK_H –
MODCK[1–3]
Input Clock
Frequency
(PCI)2,3
CPM
Multiplication
Factor2
CPM
Frequency
Core
Multiplication
Factor
Core
Frequency4
Bus Division
Factor
60x Bus
Frequency5
相關(guān)PDF資料
PDF描述
MPC8264AZUMIBX 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480
MPC8264AZUPIBX 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
MPC8265ACZUMHBC 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480
MPC8260ACZUIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
MPC8260AZUIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
相關(guān)代理商/技術(shù)參數(shù)
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