參數(shù)資料
型號： MPC8271CVRTIEA
廠商： Freescale Semiconductor
文件頁數(shù)： 33/61頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 516-PBGA
標準包裝： 40
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應商設備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
39
Clock Configuration Modes
1100_101
50.0
66.7
6
300.0 400.0
4
400.0 533.3
3
100.0 133.3
1100_110
50.0
66.7
6
300.0 400.0
4.5
450.0 599.9
3
100.0 133.3
1100_111
50.0
66.7
6
300.0 400.0
5
500.0 666.6
3
100.0 133.3
1101_000
50.0
66.7
6
300.0 400.0
5.5
550.0 733.3
3
100.0 133.3
1101_001
50.0
66.7
6
300.0 400.0
3.5
420.0 559.9
2.5
120.0 160.0
1101_010
50.0
66.7
6
300.0 400.0
4
480.0 639.9
2.5
120.0 160.0
1101_011
50.0
66.7
6
300.0 400.0
4.5
540.0 719.9
2.5
120.0 160.0
1101_100
50.0
66.7
6
300.0 400.0
5
600.0 799.9
2.5
120.0 160.0
1110_000
50.0
66.7
5
250.0 333.3
2.5
312.5 416.6
2
125.0 166.7
1110_001
50.0
66.7
5
250.0 333.3
3
375.0 500.0
2
125.0 166.7
1110_010
50.0
66.7
5
250.0 333.3
3.5
437.5 583.3
2
125.0 166.7
1110_011
50.0
66.7
5
250.0 333.3
4
500.0 666.6
2
125.0 166.7
1110_100
50.0
66.7
5
250.0 333.3
4
333.3 444.4
3
83.3
111.1
1110_101
50.0
66.7
5
250.0 333.3
4.5
375.0 500.0
3
83.3
111.1
1110_110
50.0
66.7
5
250.0 333.3
5
416.7 555.5
3
83.3
111.1
1110_111
50.0
66.7
5
250.0 333.3
5.5
458.3 611.1
3
83.3
111.1
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
1 The “l(fā)ow” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
2 PCI_MODCK determines the PCI clock frequency range. See Table 20 for lower range configurations.
3 MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
4 CPM multiplication factor = CPM clock/bus clock
5 CPU multiplication factor = Core PLL multiplication factor
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1,2 (continued)
Mode3
PCI Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3]
Low
High
Low
High
Low
High
Low
High
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