參數(shù)資料
型號(hào)： MPC8280ZUUPEA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 81/83頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 480-TBGA
標(biāo)準(zhǔn)包裝： 21
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 450MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤
其它名稱： MPC8280ZUUPE
MPC8280ZUUPE-ND
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
82
Freescale Semiconductor
Document Revision History
0.3
6/2003
Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the
MPC8275VR have local bus support.
References to “G2 core” changed to “G2_LE core.” See the
G2 Core Reference Manual
(G2CORERM/D).
Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5
Figure 2: New
Table 5: Addition of note 1
Table 10: Addition of
θJB and θJC. Modifications to ZU package values.
Table 12: Addition of various configurations, Modification of values. Addition of note 3.
Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.
Table 20: Addition of 66 MHZ and 100 MHz values
Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of
current note 2.
Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes
Section 6.2: Addition of note on PCI timing
Table 18, Table 32, Table 33, Table 36, Table 37: Addition of note 1 concerning minimum
operating frequencies
Addition of statement before clock tables about selection of clock configuration and input
frequency
Table 23 and Table 25: Addition of note 1 to CPM pins
0.2
11/2002
Table 25, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)
0.1
—
Initial public release
Table 27. Document Revision History (continued)
Revision
Date
Substantive Changes
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