參數(shù)資料
型號(hào): MPC8308ZQADD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 26/83頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
標(biāo)準(zhǔn)包裝: 84
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 473-LFBGA
供應(yīng)商設(shè)備封裝: 473-MAPBGA(19x19)
包裝: 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
32
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock
input’s DC requirement.
Figure 23. Single-Ended Connection (Reference Only)
10.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters for PCI Express protocol.
Table 32. SerDes Reference Clock AC Parameters
At recommended operating conditions with XCOREVDD= 1.0V ± 5%
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
2, 3
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
2, 3
Differential Input High Voltage
VIH
+200
mV
2
Differential Input Low Voltage
VIL
–200
mV
2
50
50
SD_REF_CLK
100
differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
MPC8308
33
Total 50
Assume clock driver’s
output impedance is about 16
50
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