參數(shù)資料
型號: MPC8308ZQAFD
廠商: Freescale Semiconductor
文件頁數(shù): 76/83頁
文件大小: 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
標(biāo)準(zhǔn)包裝: 84
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 473-LFBGA
供應(yīng)商設(shè)備封裝: 473-MAPBGA(19x19)
包裝: 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
78
Freescale Semiconductor
System Design Information
23.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, NVDD, GVDD and LVDD pin of the device.
These decoupling capacitors should receive their power from separate VDD, NVDD, GVDD, LVDD, and
VSS power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed
directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, NVDD, GVDD, LVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100 to 330 F (AVX TPS tantalum or Sanyo
OSCON). However, customers should work directly with their power regulator vendor for best values and
types of bulk capacitors.
23.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NVDD, GVDD, LVDD as required. Unused active high
inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, NVDD, AVDD1, AVDD2, GVDD, LVDD
and VSS pins of the device.
23.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I2C, MDIO and HRESET)
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD
or VSS. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (Figure 55). The output
impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals
NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
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