參數(shù)資料
型號(hào)： MPC8313CZQAGDA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, TEPBGAII-516
文件頁(yè)數(shù)： 19/100頁(yè)
文件大?。?/td> 1247K
代理商： MPC8313CZQAGDA
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
8.2.1.3
RMII Transmit AC Timing Specifications
Table 28 provides the RMII transmit AC timing specifications.
Figure 11 shows the RMII transmit AC timing diagram.
Figure 11. RMII Transmit AC Timing Diagram
8.2.1.4
RMII Receive AC Timing Specifications
Table 29 provides the RMII receive AC timing specifications.
Table 28. RMII Transmit AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
REF_CLK clock
tRMX
—20
—
ns
REF_CLK duty cycle
tRMXH/tRMX
35
—
65
%
REF_CLK to RMII data TXD[1:0], TX_EN delay
tRMTKHDX
2
—
10
ns
REF_CLK data clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII
transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Table 29. RMII Receive AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
REF_CLK clock period
tRMX
—20
—
ns
REF_CLK duty cycle
tRMXH/tRMX
35
—
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
ns
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK
TXD[1:0]
tRMTKHDX
tRMX
tRMXH
tRMXR
tRMXF
TX_EN
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