參數(shù)資料
型號(hào): MPC8313ECVRAFFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
文件頁(yè)數(shù): 36/100頁(yè)
文件大?。?/td> 1247K
代理商: MPC8313ECVRAFFB
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
40
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
or AC coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
Figure 24. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 25. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 26. Single-Ended Reference Clock Input DC Requirements
9.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL
(high-speed current steering logic) compatible DC coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce a signal with too large of an amplitude and may need to be
DC-biased at the clock driver output first, then followed with series attenuation resistor to reduce
the amplitude, in addition to AC coupling.
SD_REF_CLK
Vmax < 800 mV
Vmin > 0 V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD_REF_CLK
400 mV < SD_REF_CLK Input Amplitude < 800 mV
0V
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