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| 型號： | MPC8313VRAGDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516 |
| 文件頁數(shù)： | 44/100頁 |
| 文件大?。?/td> | 1247K |
| 代理商： | MPC8313VRAGDA |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
48
Freescale Semiconductor
Enhanced Local Bus
11.2
Local Bus AC Electrical Specifications
Table 46 describes the general timing parameters of the local bus interface.
Figure 36 provides the AC test load for the local bus.
Figure 36. Local Bus AC Test Load
Table 46. Local Bus General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
LALE output rise to LCLK negative edge
tLALEHOV
—3.0
ns
LALE output fall to LCLK negative edge
tLALETOT1
–1.5
—
ns
5
LALE output fall to LCLK negative edge
tLALETOT2
–5.0
—
ns
6
LALE output fall to LCLK negative edge
tLALETOT3
–4.5
—
ns
7
Local bus clock to output valid
tLBKHOV
—3
ns
3
Local bus clock to output high impedance for LAD
tLBKHOZ
—4
ns
8
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one (1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 × NVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 and tLALETOT1 should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10 pF less
than the load on LAD output pins.
6.tLBOTOT2 and tLALETOT2 should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10 pF less than
the load on LAD output pins.
7.tLBOTOT3 and tLALETOT3 should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD
output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output
Z0 = 50 Ω
NVDD/2
RL = 50 Ω
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8313VRAGDB | 功能描述:微處理器 - MPU PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8313VRAGDC | 功能描述:微處理器 - MPU 8313 REV2.2 NO ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8313VRGDD | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313VRGDDB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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