參數(shù)資料
型號(hào)： MPC8313ZQADD
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 7/99頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 516PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 267MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 516-PBGAPGE（27x27）
包裝： 托盤
配用： MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) when
GVDD(typ) = 1.8 V.
This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49
GV
DD
0.51
GV
DD
V2
I/O termination voltage
VTT
MVREF –0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF +0.125
GVDD +0.3
V
—
Input low voltage
VIL
–0.3
MVREF –0.125
V
—
Output leakage current
IOZ
–9.9
9.9
A4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
2.3
2.7
V
1
I/O reference voltage
MVREF
0.49
GV
DD
0.51
GV
DD
V2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.15
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF –0.15
V
—
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