參數(shù)資料
型號: MPC8313ZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, TEPBGAII-516
文件頁數(shù): 18/100頁
文件大小: 1247K
代理商: MPC8313ZQAGD
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
24
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 9 provides the AC test load for TSEC.
Figure 9. TSEC AC Test Load
Figure 10 shows the MII receive AC timing diagram.
Figure 10. MII Receive AC Timing Diagram RMII AC Timing Specifications
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
Table 27. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Output
Z0 = 50 Ω
LVDDA/2 or LVDDB/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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