參數(shù)資料
型號: MPC8343CVRAGDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件頁數(shù): 75/79頁
文件大?。?/td> 992K
代理商: MPC8343CVRAGDB
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
77
Document Revision History
23 Document Revision History
Table 64 provides a revision history of this document.
Table 64. Document Revision History
Rev.
Number
Date
Substantive Change(s)
10
11/2010
In Table 51, added overbar to LCS[4] and LCS[5] signals. In Table 51 added note for pin LGPL4.
In Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins.
9
05/2010
In Table 25 through Table 26, changed VIL(min) to VIH(max) to (20%–80%).
8
5/2009
and PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.
In Table 53, added two columns for the DDR1 and DDR2 memory bus frequency.
In Table 62, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1
and DDR2.
7
2/2009
Added footnote 6 to Table 7.
In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.
In Table 35, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock
in DLL bypass mode). Similarly, made the same correction to Figure 17, Figure 19, and Figure 20
for output signals.
Added footnote 10 to Table 51.
In Table 51, updated note 11 to say the following: “SEC1_TXD[3] is required an external pull-up
resistor. For proper functionality of the device, this pin must be pulled up or actively driven high
during a hard reset. No external pull-down resistors are allowed to be attached to this net.”
In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
In Table 62, updated note 1 to say the following: “For temperature range = C, processor frequency
is limited to 400 with a platform frequency of 266.”
6
4/2007
In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and
added USB to the seventh row.
In Section 21.7, “Pull-Up Resistor Requirements,“ deleted last two paragraphs and after first
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
5
3/2007
Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to tCISKEW
and deleted original note 3; renumbered the remaining notes.
In Figure 38, “JTAG Interface Connection,” updated with new figure.
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
4
12/2006
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified Tddkhds for 333 MHz
from 900 ps to 775 ps.
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MPC8343EA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications