參數(shù)資料
型號: MPC8343CZQAGDX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁數(shù): 66/92頁
文件大小: 987K
代理商: MPC8343CZQAGDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
69
Table 45 provides the operating frequencies for the MPC8343E PBGA under recommended operating
conditions (see).
Table 45. Operating Frequencies for PBGA
Characteristic 1
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the
resulting
ccb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum
or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and
SCCR[USBMPHCM] must be programmed such that the maximum internal operating frequency of the
Security core and USB modules will not exceed their respective value listed in this table.
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (
core_clk)
200–266
200–333
200–400
MHz
Coherent system bus frequency
(
csb_clk)
100–333
MHz
DDR memory bus frequency
(MCLK) 2
2
The DDR data rate is 2x the DDR memory bus frequency.
100–166.67
MHz
Local bus frequency
(LCLK
n) 3
3
The local bus frequency is 1/2, 1/4, or 1/8 of the
lbiu_clk frequency (depending on LCCR[CLKDIV]) which
is in turn 1x or 2x the
ccb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or
PCI_CLK)
25–66
MHz
Security core maximum internal
operating frequency
133
MHz
USB_DR, USB_MPH maximum
internal operating frequency
133
MHz
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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