參數(shù)資料
型號: MPC8343ECZQADD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁數(shù): 36/84頁
文件大小: 1428K
代理商: MPC8343ECZQADD
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
41
I
2C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8343E.
12.1
I2C DC Electrical Characteristics
Table 34 provides the DC electrical characteristics for the I2C interface of the MPC8343E.
12.2
I2C AC Electrical Specifications
Table 35 provides the AC timing parameters for the I2C interface of the MPC8343E. Note that all values
refer to VIH(min) and VIL(max) levels (see Table 34).
Table 34. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD +0.3
V
Input low voltage level
VIL
–0.3
0.3
× OVDD
V
Low level output voltage
VOL
00.2
× OVDD
V1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
050
ns
3
Input current each I/O pin (input voltage is between
0.1
× OVDD and 0.9 × OVDD(max)
II
–10
10
μA4
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8349E Integrated Host Processor Family Reference Manual, for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
Table 35. I2C AC Electrical Specifications
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0400
kHz
Low period of the SCL clock
tI2CL
1.3
μs
High period of the SCL clock
tI2CH
0.6
μs
Setup time for a repeated START condition
tI2SVKH
0.6
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
μs
Data setup time
tI2DVKH
100
ns
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
02
0.93
μs
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