參數(shù)資料
型號(hào): MPC8343EVRADDX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件頁(yè)數(shù): 23/92頁(yè)
文件大小: 987K
代理商: MPC8343EVRADDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
3
Overview
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 820.3x, 802.3z, 802.3 AC compliant controllers
— Support for different Ethernet physical interfaces:
– 1000 Mbps IEEE 802.3 RGMII, 802.3z RTBI, full-duplex
– 10/100 Mbps IEEE 802.3 MII full- and half-duplex
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFO’s per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
— PCI specification Revision 2.2 compatible
— Data bus width:
32-bit data PCI interface that operates at up to 66 MHz, or
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode supported on PCI interface
— Support for PCI to memory and memory to PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor to PCI and PCI to memory writes
— On-chip arbitration, supporting 5 masters on PCI
— Support for accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle support when target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs). The execution units are:
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
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